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data sheet ics813n252bki-09 revision b january 18, 2013 1 ?2013 integrated device technology, inc. vcxo jitter attenuator & femtoclock ? multiplier ICS813N252I-09 general description the ICS813N252I-09 is a pll based synchronous multiplier that is optimized for pdh or sonet to ethernet clock jitter attenuation and frequency translation. the device contains two internal frequency multiplication stages that are cascad ed in series. the first stage is a vcxo pll that is optimized to provide reference clock jitter attenuation. the second stage is a femtoclock? frequency multiplier that provides the low jitter, high frequency ethernet output clock that easily meets gigabit and 10 gigabit ethernet jitter requirements. pre-divider and output divider multiplication ratios are selected using device selection control pins. the multiplication ratios are optimized to support most common clock rates used in pdh, sonet and ethernet applications. the vcxo requires the use of an external, inexpensive pullable crystal. the vcxo uses external passive loop filter components which allows configuration of the pll loop bandwidth and damping characteristics. the device is packaged in a space-saving 32-vfqfn package and supports industrial temperature range. features ? two lvpecl output pairs each output supports independent frequency selection at 25mhz, 125mhz, 156.25mhz and 312.5mhz ? two differential inputs support the following input types: lvpecl, lvds, lvhstl, sstl, hcsl ? accepts input frequencies from 8khz to 155.52mhz including 8khz, 1.544mhz, 2.048mhz, 19.44mhz, 25mhz, 77.76mhz, 125mhz and 155.52mhz ? attenuates the phase jitter of the input clock by using a low-cost pullable fundamental mode vcxo crystal ? vcxo pll bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection ? femtoclock frequency multiplier provides low jitter, high frequency output ? absolute pull range: 50ppm ? femtoclock vco frequency: 625mhz ? rms phase jitter @ 125mhz, using a 25mhz crystal (12khz ? 20mhz): 0.25ps (typical) and 0.35ps (maximum) ? 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 lf1 lf0 iset v ee clk_sel v cc reserved v ee v ee nqb qb v cco nqa qa v ee odasel_0 pdsel_2 pdsel_1 pdsel_0 v cc v cca odbsel_1 odbsel_0 odasel_1 xtal_in xtal_out clk0 nclk0 v cc clk1 nclk1 v ccx pin assignment ICS813N252I-09 32 lead vfqfn 5mm x 5mm x 0.925mm package body 3.15mm x 3.15 mm epad k package top view
ics813n252bki-09 revision b january 18, 2013 2 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier block diagram charge pump vcxo phase detector output divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 output divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 vcxo feedback divider 3125 vcxo input pre-divider vcxo jitter attenuation pll xtal_in xtal_out lf1 lf0 iset loop filter odasel_[1:0] clk0 pdsel_[2:0] nclk0 0 1 25mhz 2 2 qb nqb odbsel_[1:0] femtoclock pll 625mhz 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 clk1 nclk1 clk_sel pulldown pulldown pulldown pullup pu/pd pu/pd qa nqa 111 = 19440 (default) pulldown pulldown
ics813n252bki-09 revision b january 18, 2013 3 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 lf1, lf0 analog input/output loop filter connection node pins. lf0 is the output. lf1 is the input. 3 iset analog input/output charge pump current setting pin. 4, 8, 18, 24 v ee power negative supply pins. 5 clk_sel input pulldown input clock select . when high selects clk1, nclk1. when low, selects clk0, nclk0. lvcmos / lvttl interface levels. 6, 12, 27 v cc power core supply pins. 7 reserved reserved reserved pin. do not connect. 9, 10, 11 pdsel_2, pdsel_1, pdsel_0 input pullup pre-divider select pins. lvcmos/lvttl interface levels. see table 3a. 13 v cca power analog supply pin. 14, 15 odbsel_1, odbsel_0 input pulldown frequency select pins for bank b output. see table 3b. lvcmos/lvttl interface levels. 16, 17 odasel_1, odasel_0 input pulldown frequency select pins for bank a output. see table 3b. lvcmos/lvttl interface levels. 19, 20 qa, nqa output differential bank a clock outputs. lvpecl interface levels. 21 v cco power output supply pin. 22, 23 qb, nqb output differential bank b clock outputs. lvpecl interface levels. 25 nclk1 input pullup/ pulldown inverting differential clock input. v cc /2 bias voltage when left floating. 26 clk1 input pulldown non-inverting differential clock input. 28 nclk0 input pullup/ pulldown inverting differential clock input. v cc /2 bias voltage when left floating. 29 clk0 input pulldown non-inverting differential clock input. 30, 31 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input. xtal_out is the output. 32 v ccx power power supply pin for vcxo charge pump. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics813n252bki-09 revision b january 18, 2013 4 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier function tables table 3a. pre-divider selection function table table 3b. output divider function table inputs pre-divider value pdsel_2 pdsel_1 pdsel_0 000 1 001 193 010 256 0 1 1 2430 1 0 0 3125 1 0 1 9720 1 1 0 15625 1 1 1 19440 (default) inputs output divider value odxsel_1 odxsel_0 0 0 25 (default) 01 5 10 4 11 2
ics813n252bki-09 revision b january 18, 2013 5 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier table 3c. frequency function table input frequency (mhz) pre-divider value vcxo frequency (mhz) femtoclock feedback divider value femtoclock vco frequency (mhz) output divider value output frequency (mhz) 0.008 1 25 25 625 25 25 0.008 1 25 25 625 5 125 0.008 1 25 25 625 4 156.25 0.008 1 25 25 625 2 312.5 1.544 193 25 25 625 25 25 1.544 193 25 25 625 5 125 1.544 193 25 25 625 4 156.25 1.544 193 25 25 625 2 312.5 2.048 256 25 25 625 25 25 2.048 256 25 25 625 5 125 2.048 256 25 25 625 4 156.25 2.048 256 25 25 625 2 312.5 19.44 2430 25 25 625 25 25 19.44 2430 25 25 625 5 125 19.44 2430 25 25 625 4 156.25 19.44 2430 25 25 625 2 312.5 25 3125 25 25 625 25 25 25 3125 25 25 625 5 125 25 3125 25 25 625 4 156.25 25 3125 25 25 625 2 312.5 77.76 9720 25 25 625 25 25 77.76 9720 25 25 625 5 125 77.76 9720 25 25 625 4 156.25 77.76 9720 25 25 625 2 312.5 125 15625 25 25 625 25 25 125 15625 25 25 625 5 125 125 15625 25 25 625 4 156.25 125 15625 25 25 625 2 312.5 155.52 19440 25 25 625 25 25 155.52 19440 25 25 625 5 125 155.52 19440 25 25 625 4 156.25 155.52 19440 25 25 625 2 312.5
ics813n252bki-09 revision b january 18, 2013 6 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvpecl power supply dc characteristics, v cc = v cco = v ccx = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = v cco = v ccx = 3.3v 5%, t a = -40c to 85c item rating supply voltage, v cc 3.63v inputs, v i xtal_in other inputs 0v to v cc -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma package thermal impedance, ? ja 37? c/w (0 mps) storage temperature, t stg -65 ?c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.20 3.3 v cc v v cco output supply voltage 3.135 3.3 3.465 v v ccx charge pump supply voltage 3.135 3.3 3.465 v i ee power supply current 200 ma i cca analog supply current 20 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk_sel, odasel_[0:1], odbsel_[0:1] v cc = v in = 3.465v 150 a pdsel_[0:2] v cc = v in = 3.465v 10 a i il input low current clk_sel, odasel_[0:1], odbsel_[0:1] v cc = 3.465v, v in = 0v -10 a pdsel_[0:2] v cc = 3.465, v in = 0v -150 a
ics813n252bki-09 revision b january 18, 2013 7 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier table 4c. differential dc characteristics, v cc = v cco = v ccx = 3.3v 5%, t a = -40c to 85c note 1: common mode voltage is defined at the cross point. table 4d. lvpecl dc characteristics, v cc = v cco = v ccx = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco ? 2v. see parameter measurement information section, 3.3v output load test circuit. ac electrical characteristics table 5. ac characteristics, v cc = v cco = v ccx = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth. refer to vcxo-pll loop bandwidth selection table. note 1: refer to the phase noise plot. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output diffe rential cross points. note 4: lock time measured from power-up to stable output frequency. symbol parameter test conditio ns minimum typical maximum units i ih input high current clk0, nclk0, clk1, nclk1 v cc = v in = 3.465v 150 a i il input low current clk0, clk1 v cc = 3.465v, v in = 0v -10 a nclk0, nclk1 v cc = 3.465v, v in = 0v -150 a v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage; note 1 v ee v cc ? 0.85 v symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.10 v cco ? 0.75 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units f in input frequency 0.008 155.52 mhz f out output frequency 25 312.5 mhz t jit(?) rms phase jitter, (random), note 1 125mhz f out , 25mhz crystal, integration range: 12khz ? 20mhz 0.25 0.35 ps t jit(pk-pk) peak-to-peak jitter 1e-12 ber 25 ps t sk(o) output skew; note 2, 3 25 ps t r / t f output rise/fall time 20% to 80% 140 400 ps odc output duty cycle 48 52 % t lock vcxo & femtoclock pll lock time; note 4 6s
ics813n252bki-09 revision b january 18, 2013 8 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier typical phase noise noise power dbc hz offset frequency (hz)
ics813n252bki-09 revision b january 18, 2013 9 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier parameter measureme nt information 3.3v lvpecl output load test circuit rms phase jitter output rise/fall time differential input level output skew output duty cycle/pulse width/period scope qx nqx v ee 2v -1.3v0.165v v cc, v cco v cca v ccx 2v 2v offset frequency f 1 f 2 phase noise plot area under curve defined by the offset frequency markers rms phase jitter = noise power 2 * * ? 1 * 20% 80% 80% 20% t r t f v swing qa, qb nqa, nqb nclk[0:1] clk[0:1] v cc v ee v cmr cross points v pp t sk(o) qx nqx qy nqy nqa, nqb qa, qb t pw t period t pw t period odc = x 100%
ics813n252bki-09 revision b january 18, 2013 10 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier parameter measurement in formation, continued vcxo & femtoclock pll lock time applications information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perform ance, power supply isolation is requir ed. the ICS813N252I-09 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca, v cco and v ccx should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional 10 ? resistor along with a 10 ? f bypass capacitor be connected to the v cca pin. figure 1. power supply filtering v cc v ccx v cca 3.3v 10 10 10f .01f .01f 10f .01f
ics813n252bki-09 revision b january 18, 2013 11 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. similarly, if the input clock swing is 1.8v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 0.9v. it is recommended to always use r1 and r2 to provide a known v 1 voltage. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the su m of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be in creased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels
ics813n252bki-09 revision b january 18, 2013 12 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input dri ven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 *r4 33 clk nclk 3.3v 3.3v zo = 50 zo = 50 differential input r1 50 r2 50 *optional ? r3 and r4 can be 0 clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50 clk nclk differential input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics813n252bki-09 revision b january 18, 2013 13 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl output pairs c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current pa th to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 r2 50 rtt z o = 50 z o = 50 + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 r2 84 3.3v r3 125 r4 125 z o = 50 z o = 50 lvpecl input 3.3v 3.3v + _
ics813n252bki-09 revision b january 18, 2013 14 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics813n252bki-09 revision b january 18, 2013 15 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier application sche matic example figure 6 shows an example of ICS813N252I-09 application schematic. in this example, the device is operated at v cc = v ccx = v cco = 3.3v. the decoupling capacitor should be located as close as possible to the power pin. the input is driven by a 3.3v lvpecl driver. two examples of terminations are shown in this schematic. an optional 3-pole filter can also be used for additional spur reduction. it is recommended that the loop filter components be laid out for the 3-pole option. this will also allo w the 2-pole filter to be used. figure 6. ICS813N252I-09 application schematic lvpecl optional y-termination r16 50 ru2 not install c4 0.1u rs 470k vcco r1 125 r10 133 clk0 odbsel_1 nclk0 vcc qb c8 0.1u r12 10 nqa r11 133 zo = 50 ohm pdsel_2 clk_sel r7 84 lf r3 84 rs 470k c1 tu n e vcc xtal_out r13 82.5 r2 125 3.3v + - set logic input to '1' u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 lf1 lf0 iset vee clk_sel vcc reserved vee pdsel_2 pdsel_1 pdsel_0 vcc vcca odbsel_1 odbsel_0 odasel_1 odasel_0 vee qa nqa vcco qb nqb vee vccx xtal_in xtal_out clk0 nc lk0 vcc clk1 nc lk1 cp 0.002uf vcc cp 0.002uf zo = 50 vcc zo = 50 x1 to logic input pins nclk1 r17 50 r4 84 cs 0.2uf clk0 r6 125 r18 50 zo = 50 ohm 2-pole loop filter for mid bandwidth setting vcc pdsel_0 vcc = vccx = vcco= 3.3v vccx lvpecl termination vcc clk1 r5 125 c2 tu n e c9 0.1u vcca odasel_0 nqb r9 tbd k nc lk0 c10 0.01u vcc ru1 1k lf lvpecl driv er zo = 50 set logic input to '0' xtal_in vcc vcc r15 2.21k rd1 not install odbsel_0 lf qa to logic input pins logic control input examples rd2 1k c11 10u c5 0.01u r14 82.5 pdsel_1 + - odasel_1 3-pole loop filter example - (optional) c3 tbd pf vcc r19 10 zo = 50 ohm lf cs 0.2uf c7 0.1u zo = 50 ohm r8 85 lvpecl driv er zo = 50 c6 10u
ics813n252bki-09 revision b january 18, 2013 16 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier vcxo-pll e xternal c omponents choosing the correct external components and having a proper printed circuit board (pcb) layout is a key task for quality operation of the vcxo-pll. in choosing a crystal, special precaution must be taken with the package and load capacitance (c l ). in addition, frequency, accuracy and temperature range must also be considered. since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like hc49 be used. generally, a metal-canned package has a larger pulling range than a surface mounted device (smd). for crystal selection information, refer to the vcxo crystal selection application note. the crystal?s load capacitance c l characteristic determines its resonating frequency and is closely related to the vcxo tuning range. the total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, ic package lead capacitance, internal varactor capacitance and any installed tuning capacitors (c tune ). if the crystal c l is greater than the total external capacitance, the vcxo will oscillate at a higher frequency than the crystal specification. if the crystal c l is lower than the total external capacitance, the vcxo will oscillat e at a lower frequency than the crystal specification. in either case, the absolute tuning range is reduced. the correct value of c l is dependant on the characteristics of the vcxo. the recommended c l in the crystal parameter table balances the tuning range by centering the tuning curve. the frequency of oscillation in the third overtone mode is not necessarily at exactly three times the fundamental frequency. the mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental. the oscillator circuit may excite both the fundamental and overtone modes simultaneously. this will cause a nonlinearity in the tuning curve. this potential problem is why vcxo crystals are required to be tested for absence of any activity inside a 200ppm window at three times the fundamental frequency. refer to c and f l_3ovt_spurs in the crystal characteristics table . the crystal and external loop filter components should be kept as close as possible to the device. loop filter and crystal traces should be kept short and separated from each other. other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. vcxo characteristics table vcxo-pll loop bandwidth selection table note: when configuring the ICS813N252I-09 with pll loop bandwidth less than 75hz, it is recommended that clk1, nclk1 input be used as the only reference clock. in systems where both reference clocks are used, it is recommended to have pll loop bandwidths of 75hz or greater. crystal characteristics lf0 lf1 iset xtal_in xtal_out r s c s c p r set c tune c tune 25mhz symbol parameter typical units k vcxo vcxo gain 4.4 khz/v c v_low low varactor capacitance 8 pf c v_high high varactor capacitance 16 pf bandwidth crystal frequency (mhz) m r s (k ? ) c s (f) c p (f) r set (k ? ) 8hz (low) 25 3125 680 0.20 0.002 22 20hz (mid) 25 3125 470 0.20 0.002 5 75hz (high) 25 3125 680 0.02 0.003 2.2 symbol parameter test conditions minimum typical maximum units mode of oscillation fundamental f n frequency 25 mhz f t frequency tolerance 20 ppm f s frequency stability 20 ppm operating temperature range -40 85 0 c c l load capacitance 10 pf c o shunt capacitance 4 pf c o / c 1 pullability ratio 220 240 f l_3ovt 3 rd overtone f l 200 ppm f l_3ovt_spurs 3 rd overtone f l spurs 200 ppm esr equivalent series resistance 20 ? drive level 1mw aging @ 25 0 c one year 3 ppm ten year 10 ppm
ics813n252bki-09 revision b january 18, 2013 17 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier power considerations this section provides information on power dissipati on and junction temperature for the ICS813N252I-09. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS813N252I-09 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 200ma = 693mw ? power (outputs) max = 31.55mw/loaded output pair if all outputs are loaded, the total power is 2 * 31.55mw = 63.10mw total power_ max (3.3v, with all outputs switching) = 693mw + 63.10mw = 756.10mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliabil ity of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 37c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.756w * 37c/w = 113c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 32 lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 37.0c/ w 32.4c/w 29c/w
ics813n252bki-09 revision b january 18, 2013 18 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate power dissipation per output due to l oading, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.75v (v cco_max ? v oh_max ) = 0.75v ? for logic low, v out = v ol_max = v cco_max ? 1.6v (v cco_max ? v ol_max ) = 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.75v)/50 ? ] * 0.75v = 18.75mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l] * (v cco_max ? v ol_max ) = [(2v ? 1.6v)/50 ? ] * 1.6v = 12.80mw total power dissipation per output pair = pd_h + pd_l = 31.55mw v out v cco v cco - 2v q1 rl 50
ics813n252bki-09 revision b january 18, 2013 19 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier reliability information table 7. ? ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for ICS813N252I-09 is: 22,280 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 37.0c/w 32.4c/w 29c/w
ics813n252bki-09 revision b january 18, 2013 20 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier package outline and package dimensions package outline - k suffix for 32 lead vfqfn table 8. package dimensions reference document: jede c publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8. to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil s ingu l a tion n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there a re 2 methods of indica ting pin 1 corner a t the back of the vfqfn pa cka ge a re: 1. type a: ch a mfer on the pa ddle (nea r pin 1) 2. type c: mouse b ite on the pa ddle (nea r pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00 . 0 5 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ics813n252bki-09 revision b january 18, 2013 21 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier ordering information table 9. ordering information part/order number marking package shipping packaging temperature 813n252bki-09lf ics252bi09l ?lead-free? 32 lead vfqfn tray -40 ? c to 85 ?c 813n252bki-09lft ics252bi09l ?lead-free? 32 lead vfqfn 2500 tape & reel -40 ? c to 85 ?c
ics813n252bki-09 revision b january 18, 2013 22 ?2013 integrated device technology, inc. ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier revision history sheet rev table page description of change date a 6 supply voltage, v cc. rating changed from 4.5v min. to 3.63v per errata nen-11-03. 6/08/11 b t9 11 16 20 21 per pcn #n1210-01 changed revision marking from ?a? to ?b? in page footer and ordering information table. updated wiring the differential input to accept single-ended levels application note. vcxo-pll external components application note. vcxo-pll loop bandwidth selection table - added note. crystal characteristics - added ?ten year? spec to aging row. updated package outline. ordering information table - changed revision marking from ?a? to ?b?; deleted tape & reel count; deleted note. 1/18/13
ICS813N252I-09 data sheet vcxo jitter attenuator & femtoclock ? multiplier disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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